1. Field of the Invention
The present invention relates to a method and apparatus for detecting and correcting faults on busses, and more particularly relates to a method and apparatus for online detection and correction of faults affecting system-on-chip busses.
2. Description of Related Art
In recent generations of application specific integrated circuit (ASIC) technologies, the width and pitch of interconnect metal have been decreasing while clock frequencies have been increasing. This raises concern about on-chip crosstalk effects due to the ability of signals traveling on one wire to affect the speed of signals traveling on adjacent or victim wires. In extreme cases, crosstalk can cause signals to spike on the victim wires.
Crosstalk is related to the cross-coupling capacitance and inductance between interconnects. It is becoming more and more important due to the sharply increasing number of components and cores in a single chip that create the need for global interconnects. Long interconnects increase tremendously the rate of errors due to crosstalk. This problem with long interconnects will dominate future System-On-Chip (SOCs).
Due to the continuously shrinking geometry of semiconductor chips, the width of the wires is reduced, thereby increasing the wires' resistance; as a consequence, the delay introduced by wires is increasing. One solution to this problem is to increase the thickness of the wires in order to increase their cross-section, thereby reducing the wires' resistance. However, this solution increases crosstalk problems because wires on different layers have less space between them. Another solution is to use copper wires which have a resistivity lower that that of aluminum wires. Although some companies (in particular IBM) have already migrated most of its microprocessors to copper wires, this solution only postpones the cross-talk problem by several years.
Crosstalk has been extensively analyzed in the past and several design techniques have been proposed, especially at the physical design level. See for example: Zhou et al., “Global Routing with Crosstalk Constraints,” Proc. Design Automation Conf., pp. 374-77, Jun. 1998; and Z. Chen et al., “Crosstalk Minimization in Three-Layer HVH Channel Routing,” Proc. IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 38-42, 1997. The basic solution is to compensate for crosstalk effects in the wire delay calculation, and integrate the compensation into the layout process.
The integration is generally implemented by factoring in a coupling capacitance extracted from the layout and by using a worst-case signal-switching scenario. Conservative factors are chosen after analyzing crosstalk on a representative cross section of the layout using different routing pitches on signal interconnect metal. The goal is to find the right balance between metal pitch, area used, and chip timing. Hopefully, with a slight increase in chip area, it will be possible to design crosstalk free layouts.
However, the problem is that with the continuously increasing complexity of systems, it is not always possible to adopt very conservative layout rules to eliminate the need for crosstalk and electromigration analysis. Therefore, alternative solutions must be found.
Although some analysis tools have recently appeared (see for example, X. Bay, et al. “Self-Test Methodology for At-Speed Testing of Crosstalk in Chip Interconnects,” Proc. Design Automation Conf., pp. 619-24, Jun. 2000), there is still an urgent need for analysis and synthesis tools able to reduce the amount of overhead required to minimize signal integrity problems.
One recently proposed method presented a self-checking detection and diagnosis scheme for several kinds of faults (transient, delay and crosstalk) affecting bus lines of synchronous systems. See C. Metra et al., “Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines, IEEE Trans. Computers, vol. 49, pp. 560-74, Jun. 2000. An important difference with respect to the present invention is that, unlike the Metra et al. method, the present invention proposes a system-level approach that is able to leverage CMOS fabrication process parameters and chip characterization parameters in order to extract a list of temporal faults to be applied to the system being designed during a high-level co-simulation session.